Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
A VLSI layout for a pipelined Dadda multiplier
ACM Transactions on Computer Systems (TOCS)
A Single Chip Parallel Multiplier by MOS Technology
IEEE Transactions on Computers
Parallel Multiplication Using Fast Sorting Networks
IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
Integer Multiplication with Overflow Detection or Saturation
IEEE Transactions on Computers - Special issue on computer arithmetic
Integration, the VLSI Journal
Fast Arithmetic and Fault Tolerance in the FERMI System
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable-latency floating-point multipliers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A very high-speed CMOS 4-2 compressor using fully differential current-mode circuit techniques
Analog Integrated Circuits and Signal Processing
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a new design technique for column-compression (CC) multipliers is presented. Constraints for column compression with full and half adders are analyzed and, under these constraints, considerable flexibility for implementation of the CC multiplier, including the allocation of adders, and choosing the length of the final fast adder, is exploited. Using the example of an 8 脳 8 bit CC multiplier, we show that architectures obtained from this new design technique are more area efficient, and have shorter interconnections than the classical Dadda CC multiplier. We finally show that our new technique is also suitable for the design of twos complement multipliers.