A 40-ns 17-Bit by 17-Bit Array Multiplier
IEEE Transactions on Computers
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
IEEE Transactions on Computers
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
A new parallel multiplication algorithm and its VLSI implementation
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
A Single Chip Parallel Multiplier by MOS Technology
IEEE Transactions on Computers
Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I/sup 2/L Technology
IEEE Transactions on Computers
A New Design Technique for Column Compression Multipliers
IEEE Transactions on Computers
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography
ACM SIGARCH Computer Architecture News
| Hi-index | 15.00 |
Algorithms for the parallel multiplication of two n- bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n-cell delays for one n-bit 脳 n-bit multiplication, are compared to a straightforward iterative array algorithm having a 2n-cell delay and its higher radix version having an n-cell delay.