Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Using complementation and resequencing to minimize transitions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
Inverse polarity techniques for high-speed/low-power multipliers
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
A VLSI layout for a pipelined Dadda multiplier
ACM Transactions on Computer Systems (TOCS)
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Low Power Digital CMOS Design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
A New Architecture for 2's Complement Gray Encoded Array Multiplier
Proceedings of the 15th symposium on Integrated circuits and systems design
A New Architecture for Signed Radix-2m Pure Array Multipliers
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Binary Multiplication Radix-32 and Radix-256
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses
Proceedings of the conference on Design, automation and test in Europe
Power Efficient Arithmetic Operand Encoding
Proceedings of the 14th symposium on Integrated circuits and systems design
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
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We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. The architecture uses radix-2^m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. Each group of m bits is encoded in Gray code, thus potentially enabling a further reduction of the switching activity both internally and at the inputs. The flexibility of our architecture allows for the easy construction of multipliers for different values of m, as opposed to the Booth multiplier for which implementations for m2 are complex. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the Modified Booth multiplier. We have additionally implemented pipelined versions of these architectures. The results we present show that the proposed architecture with radix-4 also compares favorably in performance and power with the Modified Booth multiplier in the pipelined version.