A New Architecture for Signed Radix-2m Pure Array Multipliers

Authors:
Affiliations:
Venue:
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Year:
2002

Citing 0
Cited 4

A new array architecture for signed multiplication using Gray encoded radix-2m operands

Integration, the VLSI Journal
Design of low complexity digital FIR filters

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization

SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization

Proceedings of the 24th symposium on Integrated circuits and systems design

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This architecture is extended for radix-2m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. The flexibility of our architecture allows for the easy construction of multipliers for different values of m, as opposed to the Booth architecture for which implementations for m