IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
A New Architecture for Signed Radix-2m Pure Array Multipliers
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
An approximate algorithm for the multiple constant multiplications problem
Proceedings of the 21st annual symposium on Integrated circuits and system design
Optimization of area under a delay constraint in multiple constant multiplications
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applications, such as finite impulse response (FIR) filters and linear transforms. Although low-complexity high-performance multiplier architectures have been proposed for the constant multiplications, the area and delay optimization of the MCM operation has often been accomplished by synthesizing the constant multiplications using only addition/subtraction and shifting operations in the shift-adds architecture. To obtain further reductions in area, delay, and power consumption in the shift-adds design of the MCM operation, efficient high-level algorithms have also been proposed. In this paper, we introduce a computer-aided design tool for the synthesis of low-complexity digital FIR filters that includes both high and low level synthesis phases. In the high-level synthesis phase, the MCM operation is optimized in terms of high-level area and delay parameters and the digital FIR filter with the optimized MCM operation is implemented at gate-level in the low-level synthesis phase. It is observed from the experimental results that the design of the MCM operation in shifts-add architecture with the use of high-level algorithms achieves significant area improvements on filter implementations with respect to designs whose MCM operations are implemented in array multiplier architecture.