Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Some Optimizations of Hardware Multiplication by Constant Matrices
IEEE Transactions on Computers
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
An approximate algorithm for the multiple constant multiplications problem
Proceedings of the 21st annual symposium on Integrated circuits and system design
Area optimization algorithms in high-speed digital FIR filter synthesis
Proceedings of the 21st annual symposium on Integrated circuits and system design
Design of low complexity digital FIR filters
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Optimization of area under a delay constraint in multiple constant multiplications
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
Xquasher: a tool for efficient computation of multiple linear expressions
Proceedings of the 46th Annual Design Automation Conference
A low-complexity viterbi decoder for space-time trellis codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
Efficient shift-adds design of digit-serial multiple constant multiplications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Optimization Algorithms for the Multiplierless Realization of Linear Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding the optimal tradeoff between area and delay in multiple constant multiplications
Microprocessors & Microsystems
Integration, the VLSI Journal
SIREN: a depth-first search algorithm for the filter design optimization problem
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Reconfigurable Constant Multiplier for FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Most DSP synthesis tools perform limited architectural transformations to optimize hardware and power, Multiplications are often implemented with shift and-add operations for hardware efficiency, In this paper, we propose an optimization that combines a numerical transformation called number-splitting with a shift-and-add decomposition scheme. The numerical transformation "globally" changes the constant multipliers and the data flow-graph of the system under design, enabling implementations with fewer shifts and adds. The decomposition of multiplications into shifts and adds is such that as much intermediate computation results (partial products) can be reused as possible. The total number of operations can be reduced to 30% for two's complement encoding, yielding significant power and hardware saving.