Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Authors:
H. Ho;V. Szwarc;T. Kwasniewski
Affiliations:
Communications Research Centre, Ottawa, Canada K2H 8S2;Communications Research Centre, Ottawa, Canada K2H 8S2;Department of Electronics, Carleton University, Ottawa, Canada K1S 5B6
Venue:
Journal of Signal Processing Systems
Year:
2010

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Abstract

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12驴脳驴12 and 42驴脳驴42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.