Optimization method for broadband modem FIR filter design using common subexpression elimination
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Power optimization using divide-and-conquer techniques for minimization of the number of operations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions
Journal of VLSI Signal Processing Systems
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
Synthesis of low power folded programmable coefficient FIR digital filters (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
An Efficient IDCT Processor Design for HDTV Applications
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
Low-Power Constant-Coefficient Multiplier Generator
Journal of VLSI Signal Processing Systems
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Optimizing FPGA-Based Vector Product Designs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Small area parallel chien search architectures for long BCH codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Some Optimizations of Hardware Multiplication by Constant Matrices
IEEE Transactions on Computers
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Layout-driven architecture synthesis for high-speed digital filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coefficient optimization for area-effective multiplier-less FIR filters
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
Multiplierless implementation of rotators and FFTs
EURASIP Journal on Applied Signal Processing
Energy-efficient acceleration of MPEG-4 compression tools
EURASIP Journal on Embedded Systems
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
Complexity Reduction of Constant Matrix Computations over the Binary Field
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
An area reduction method for digital filter using redundancy of SD number system
Proceedings of the 3rd International Conference on Ubiquitous Information Management and Communication
A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Signal Processing
High-level synthesis algorithm for the design of reconfigurable constant multiplier
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
A novel FIR filter implementation using truncated MCM technique
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Techniques for avoiding sign-extension in multiple constant multiplication
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Design of multiplierless FIR filters with an adder depth versus filter order trade-off
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
Efficient shift-adds design of digit-serial multiple constant multiplications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Optimization Algorithms for the Multiplierless Realization of Linear Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding the optimal tradeoff between area and delay in multiple constant multiplications
Microprocessors & Microsystems
Optimisation of constant matrix multiplication operation hardware using a genetic algorithm
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
Efficient arithmetic sum-of-product (SOP) based multiple constant multiplication (MCM) for FFT
Proceedings of the International Conference on Computer-Aided Design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
Integration, the VLSI Journal
An Algorithm for Jointly Optimizing Quantization and Multiple Constant Multiplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A class of reconfigurable and low-complexity two-stage Nyquist filters
Signal Processing
| Hi-index | 0.04 |
Many applications in DSP, telecommunications, graphics, and control have computations that either involve a large number of multiplications of one variable with several constants, or can easily be transformed to that form. A proper optimization of this part of the computation, which we call the multiple constant multiplication (MCM) problem, often results in a significant improvement in several key design metrics, such as throughput, area, and power. However, until now little attention has been paid to the MCM problem. After defining the MCM problem, we introduce an effective problem formulation for solving it where first the minimum number of shifts that are needed is computed, and then the number of additions is minimized using common subexpression elimination. The algorithm for common subexpression elimination is based on an iterative pairwise matching heuristic. The power of the MCM approach is augmented by preprocessing the computation structure with a new scaling transformation that reduces the number of shifts and additions. An efficient branch and bound algorithm for applying the scaling transformation has also been developed. The flexibility of the MCM problem formulation enables the application of the iterative pairwise matching algorithm to several other important and common high level synthesis tasks, such as the minimization of the number of operations in constant matrix-vector multiplications, linear transforms, and single and multiple polynomial evaluations. All applications are illustrated by a number of benchmarks