Error control systems for digital communication and storage
Error control systems for digital communication and storage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complexity Reduction of Constant Matrix Computations over the Binary Field
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Nonlinear multi-error correction codes for reliable MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To implement parallel BCH (Bose-Chaudhuri-Hochquenghem) decoders in an area-efficient manner, this paper presents a novel group matching scheme to reduce the Chien search hardware complexity by 60% for BCH(2047, 1926, 23) code as opposed to only 26% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.