Decoding of Reed Solomon codes beyond the error-correction bound
Journal of Complexity
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Complexity - Special issue on coding and cryptography
Small area parallel chien search architectures for long BCH codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
FDTC '08 Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
Journal of Electronic Testing: Theory and Applications
Inversionless decoding of binary BCH codes
IEEE Transactions on Information Theory
New class of nonlinear systematic error detecting codes
IEEE Transactions on Information Theory
Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
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Multi-level cell (MLC) NAND flash memories are popular storage media because of their power efficiency and large storage density. Conventional reliable MLC NAND flash memories based on BCH codes or Reed-Solomon (RS) codes have a large number of undetectable and miscorrected errors. Moreover, standard decoders for BCH and RS codes cannot be easily modified to correct errors beyond their error correcting capability t = ⌊(d - 1/2)⌋, where d is the Hamming distance of the code. In this paper, we propose two general constructions of nonlinear multi-error correcting codes based on concatenations or generalized from Vasil'ev codes. The proposed constructions can generate nonlinear bit-error correcting or digit-error correcting codes with very few or even no errors undetected or miscorrected for all codewords. Moreover, codes generated by the generalized Vasil'ev construction can correct some errors with multiplicities larger than t without any extra overhead in area, latency, and power consumption compared to schemes where only errors with multiplicity up to t are corrected. The design of reliable MLC NAND flash architectures can be based on the proposed nonlinear multi-error correcting codes. The reliability, area overhead and the penalty in latency and power consumption of the architectures based on the proposed codes are compared to architectures based on BCH codes and RS codes. The results show that using the proposed nonlinear error correcting codes for the protection of MLC NAND flash memories can reduce the number of errors undetected or miscorrected for all codewords to be almost 0 at the cost of less than 20% increase in power and area compared to architectures based on BCH codes and RS codes.