A generalized parity function and its use in the construction of perfect codes
SIAM Journal on Algebraic and Discrete Methods
Error-control coding for computer systems
Error-control coding for computer systems
Kernels of nonlinear Hamming codes
Designs, Codes and Cryptography
Symbol error correcting codes for memory applications
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Unidirectional error correction/detection for VLSI memory
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An efficient class of SEC-DED-AUED codes
ISPAN '97 Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Journal of Complexity - Special issue on coding and cryptography
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers
Error-Correcting Codes with Byte Error-Detection Capability
IEEE Transactions on Computers
FDTC '08 Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
Non-linear residue codes for robust public-key arithmetic
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
IEEE Spectrum
New class of nonlinear systematic error detecting codes
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
Nonlinear multi-error correction codes for reliable MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose memory protection architectures based on nonlinear single-error-correcting, double-error-detecting (SEC-DED) codes. Linear SEC-DED codes widely used for design of reliable memories cannot detect and can miscorrect lots of errors with large Hamming weights. This may be a serious disadvantage for many modern technologies when error distributions are hard to estimate and multi-bit errors are highly probable. The proposed protection architectures have fewer undetectable errors and fewer errors that are miscorrected by all codewords than architectures based on linear codes with the same dimension at the cost of a small increase in the latency penalty, the area overhead and the power consumption. The nonlinear SEC-DED codes are generalized from the existing perfect nonlinear codes (Vasil'ev codes, Probl Kibern 8:375---378, 1962; Phelps codes, SIAM J Algebr Discrete Methods 4:398---403, 1983; and the codes based on one switching constructions, Etzion and Vardy, IEEE Trans Inf Theory 40:754---763, 1994). We present the error correcting algorithms, investigate and compare the error detection and correction capabilities of the proposed nonlinear SEC-DED codes to linear extended Hamming codes and show that replacing linear extended Hamming codes by the proposed nonlinear SEC-DED codes results in a drastic improvement in the reliability of the memory systems in the case of repeating errors or high multi-bit error rate. The proposed approach can be applied to RAM, ROM, FLASH and disk memories.