Measurement and Generation of Error Correcting Codes for Package Failures
IEEE Transactions on Computers
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Decoding of DBEC-TBED Reed-Solomon codes
IEEE Transactions on Computers
Fault-tolerance design of the IBM Enterprise System/9000 Type 9021 processors
IBM Journal of Research and Development
Two error-detecting and correcting circuits for space applications
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
IVEC: off-chip memory integrity protection for both security and reliability
Proceedings of the 37th annual international symposium on Computer architecture
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
Journal of Electronic Testing: Theory and Applications
A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications
IEEE Transactions on Computers
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
Automatic generation of error control codes for computer applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
Single error-correcting and double error-detecting codes capable of detecting all single byte errors are important for practical applications. They can be used to enhance the reliability and the data integrity of computer memory systems. Here we present the construction of these codes. The construction techniques are developed from the theory of orthogonal flats in finite Euclidean geometry.