Error-correcting codes for byte-organized memory systems
IEEE Transactions on Information Theory
Error-control coding for computer systems
Error-control coding for computer systems
The RISC system/6000 SMP system
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers
Code Constructions for Error Control in Byte Organized Memory Systems
IEEE Transactions on Computers
Single Byte Error Correcting Double Byte Error Detecting Codes for Memory Systems
IEEE Transactions on Computers
Error-Correcting Codes with Byte Error-Detection Capability
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications
IEEE Transactions on Computers
IEEE Transactions on Information Theory
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This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC's) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with odd-bit-per-byte error correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card.