Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard
Journal of Systems Architecture: the EUROMICRO Journal
Differential fault analysis on the ARIA algorithm
Information Sciences: an International Journal
Differential Behavioral Analysis
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
High-Performance Concurrent Error Detection Scheme for AES Hardware
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Novel PUF-Based Error Detection Methods in Finite State Machines
Information Security and Cryptology --- ICISC 2008
A compact ASIC implementation of the advanced encryption standard with concurrent error detection
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Memory Leakage-Resilient Encryption Based on Physically Unclonable Functions
ASIACRYPT '09 Proceedings of the 15th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Non-linear Error Detection for Finite State Machines
Information Security Applications
Design and implementation of robust embedded processor for cryptographic applications
Proceedings of the 3rd international conference on Security of information and networks
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
Journal of Electronic Testing: Theory and Applications
Design and characterisation of an AES chip embedding countermeasures
International Journal of Intelligent Engineering Informatics
A fault attack against the FOX cipher family
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
A comparative cost/security analysis of fault attack countermeasures
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Non-linear residue codes for robust public-key arithmetic
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Fault attack resistant cryptographic hardware with uniform error detection
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Design of reliable and secure multipliers by multilinear arithmetic codes
ICICS'09 Proceedings of the 11th international conference on Information and Communications Security
An emerging threat: eve meets a robot
INTRUST'10 Proceedings of the Second international conference on Trusted Systems
Fault detection of the macguffin cipher against differential fault attack
INTRUST'11 Proceedings of the Third international conference on Trusted Systems
LATINCRYPT'12 Proceedings of the 2nd international conference on Cryptology and Information Security in Latin America
Error detecting AES using polynomial residue number systems
Microprocessors & Microsystems
Fault analysis study of the block cipher FOX64
Multimedia Tools and Applications
Comprehensive analysis of software countermeasures against fault attacks
Proceedings of the Conference on Design, Automation and Test in Europe
Secure multipliers resilient to strong fault-injection attacks using multilinear arithmetic codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Attacks on implementations of cryptographic algorithms: side-channel and fault attacks
Proceedings of the 6th International Conference on Security of Information and Networks
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We present a method of protecting a hardwareimplementation of the Advanced Encryption Standard(AES) against a side-channel attack known as DifferentialFault Analysis attack.The method uses systematicnonlinear (cubic) robust error detecting codes.Error-detectingcapabilities of these codes depend not just onerror patterns (as in the case of linear codes) but also ondata at the output of the device which is protected by thecode and this data is unknown to the attacker since itdepends on the secret key.In addition to this, theproposed nonlinear (n,k)-codes reduce the fraction ofundetectable errors from 2{-r} to 2{-2r} as compared to thecorresponding (n,k) linear code (where n-k=r and k=r).We also present results on a FPGA implementation of theproposed protection scheme for AES as well as simulationresults on efficiency of the robust codes.