Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
IEEE Transactions on Computers
Journal of Complexity - Special issue on coding and cryptography
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Differential fault analysis on AES key schedule and some countermeasures
ACISP'03 Proceedings of the 8th Australasian conference on Information security and privacy
Optimal codes for minimax criterion on error detection
IEEE Transactions on Information Theory
New class of nonlinear systematic error detecting codes
IEEE Transactions on Information Theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Hardware implementations of cryptographic algorithms are vulnerable to fault analysis attacks. Methods based on traditional fault-tolerant architectures are not suited for protection against these attacks. To detect these attacks we propose an architecture based on robust nonlinear systematic error-detecting codes. These nonlinear codes are capable of providing uniform error detecting coverage independently of the error distributions. They make no assumptions about what faults or errors will be injected by an attacker. Architectures based on these robust constructions have fewer undetectable errors than linear codes with the same n,k. We present the general properties and construction methods of these codes as well as their application for the protection of a cryptographic devices implementing the Advanced Encryption Standard.