Optimal Robust Compression of Test Responses

Authors:
M. G. Karpovsky;P. Nagvajara
Affiliations:
-;-
Venue:
IEEE Transactions on Computers
Year:
1990

Citing 4
Cited 9

A unified view of test compression methods

IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test

IEEE Transactions on Computers
Finite Orthogonal Series in Design of Digital Devices

Finite Orthogonal Series in Design of Digital Devices

GT-EP: a novel high-performance real-time architecture

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Reducing the MISR Size

IEEE Transactions on Computers
Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard

Journal of Systems Architecture: the EUROMICRO Journal
Aliasing-Free Compaction In Testing Cores-Based System-On-Chip (SOC) Using Compatibility Of Response Data Outputs

Journal of Integrated Design & Process Science
Board-level diagnosis by signature analysis

ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Altera max plus II development environment in fault simulation and test implementation of embedded

IWDC'04 Proceedings of the 6th international conference on Distributed Computing
Fault attack resistant cryptographic hardware with uniform error detection

FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Implementation of embedded cores-based digital devices in JBits java simulation environment

CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology

Quantified Score

Hi-index	14.98

Visualization

Abstract

A compression of test responses technique for a built-in self-test (BIST) VLSI design is presented. The authors introduce the notion of a robust compression technique which incorporates prior knowledge of the statistics of fault-free responses under pseudorandom testing to achieve a guaranteed error detectability independent of a distribution of errors. The presented robust quadratic compressor requires two r-bit registers (r-bit signature) more than a multiple-input linear feedback shift register; however, it provides for equal protection against all error patterns. Therefore, quadratic compressors are optimal and robust with respect to a statistics of errors in a device under test.