Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
IEEE Transactions on Computers
Test response compaction for built-in self testing
Test response compaction for built-in self testing
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On a New Approach for Finding All the Modified Cut-Sets in an Incompatibility Graph
IEEE Transactions on Computers
IEEE Design & Test
Designing zero-aliasing space compressors: graph theory approach
MIC '07 Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control
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This paper suggests a novel approach to designing aliasing free space compactors with maximal compaction ratio utilizing concepts of strong and weak compatibilities of response data outputs together with conventional switching theory concepts of cover table and frequency ordering for detectable single stuck line faults of the circuit under test (CUT), based on the assumption of generalized sequence mergeability. The advantages of aliasing free space compaction as developed in the paper over earlier techniques are obvious since zero aliasing is achieved here without any modifications of the CUT, while the area overhead and signal propagation delay are relatively less compared to conventional parity tree linear compactors. The approach used works equally well with both deterministic compacted tests and pseudorandom test sets.