A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Programmable BIST Space Compactors
IEEE Transactions on Computers
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Optimal Space Compaction of Test Responses
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
Efficient Test-Response Compression for Multiple-Output Cicuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An improved output compaction technique for built-in self-test in VLSI circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Journal of Integrated Design & Process Science
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
IEICE - Transactions on Information and Systems
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
Designing zero-aliasing space compressors: graph theory approach
MIC '07 Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics
Implementation of embedded cores-based digital devices in JBits java simulation environment
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
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A new method is presented for designing space compactors for either deterministic testing or pseudorandom testing. A tree of elementary gates (AND, OR, NAND, NOR) is used to combine the outputs of the circuit-under-test (CUT) in a way that zero-aliasing is guaranteed with no modification of the CUT. The elementary-tree is synthesized by adding one gate at a time without introducing redundancy. The end result is a cascaded network, CUT followed by space compactor, that is irredundant and has fewer outputs than the CUT alone. All faults in the CUT and space compactor can be tested. Only the outputs of the space compactor need to be observed during testing. Experimental results are surprising; they show that very high compaction ratios can be achieved with zero-aliasing elementary-tree space compactors. Compared with parity trees and other space compactor designs that have been proposed, the method presented here requires less overhead and yet guarantees zero-aliasing.