Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Test Width Compression for Built-In Self Testing
Proceedings of the IEEE International Test Conference
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Space and time compaction schemes for embedded cores
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Design of Parameterizable Error-Propagating Space Compactors for Response Observation
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Efficient BIST TPG design and test set compaction via input reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
A narrow channel width between a circuit under test anda tester increases the testing time. In this paper, we proposea channel width compression method when the channelwidth is limited. A given test sequence is partitioned intosub-sequences, whose widths can be compressed under thelimited width. Each sub-sequence is compressed and expandedby a proposed dynamically re-configurable circuitlocated between the circuit under test and the tester. Sincethe hardware overhead depends on the number of partitionsfor a test sequence, a procedure to partition a given test sequenceinto a minimum number of sub-sequences under thechannel width limitation is proposed. Experimental resultsshow that our method can compress the width of a test sequenceinto a half through a quarter with a relatively smallnumber of partitions.