Journal of Electronic Testing: Theory and Applications
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
An Arithmetic Structure for Test Data Horizontal Compression
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
Matrix-based software test data decompression for systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Two dimensional reordering of functional test data for compression by ATE
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
MICRO: a new hybrid test data compression/ decompression scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression based on geometric shapes
Computers and Electrical Engineering
An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data
Journal of Signal Processing Systems
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The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and very efficient lossless compression technique for testing systems-on-a-chip based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest ISCAS85 and full-scanned versions of ISCAS89 benchmark circuits. In this paper, it is assumed that an embedded core will be used to execute the decompression algorithm and decompress the test data.