IEEE Spectrum
Digital compression for multimedia: principles and standards
Digital compression for multimedia: principles and standards
Journal of Electronic Testing: Theory and Applications
Matrix-Based Test Vector Decompression Using an Embedded Processor
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Deterministic Test Vector Decompression in Software Using Linear Operations
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
IEEE Transactions on Computers
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
Efficient test-data compression for IP cores using multilevel Huffman coding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ARMORY: An automatic security testing tool for buffer overflow defect detection
Computers and Electrical Engineering
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and efficient test-independent compression technique based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The test set is partitioned into blocks and then each block is encoded separately. The encoder has the choice of encoding either the 0's or the 1's in a block. In addition, it encodes a block that contains only 0's (or 1's) and x's with only 3bits. Furthermore, if the cost of encoding a block using geometric shapes is higher than the original cost of the block, the block is stored as is without encoding. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest full-scanned versions of ISCAS89 benchmark circuits. The proposed technique achieves significantly higher compression in comparison to other test-independent compression techniques reported in the literature.