Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Detection of Bridge Defects with Stuck-at Tests
IEICE - Transactions on Information and Systems
Customizing pattern set for test power reduction via improved X-identification and reordering
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Test data compression based on geometric shapes
Computers and Electrical Engineering
Integration, the VLSI Journal
On testing timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.