Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Proceedings of the IEEE International Test Conference 2001
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Experimental Evaluation of Scan Tests for Bridges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Systematic Defects in Deep Sub-Micron Technologies
ITC '04 Proceedings of the International Test Conference on International Test Conference
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
ITC '04 Proceedings of the International Test Conference on International Test Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compact test sets for high defect coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. In this paper we propose a method to detect bridge defects with a test set initially generated for stuck-at faults in a full scan sequential circuit. The proposed method doesn't add new test vectors to the test set but modifies test vectors. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND-type, OR-type and 4-way bridging faults, respectively. Experimental results show that the proposed method increases the defect coverage.