Proceedings of the conference on Design, automation and test in Europe
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On the properties of the input pattern fault model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Measure of Quality for n-Detection Test Sets
IEEE Transactions on Computers
N-detection under transparent-scan
Proceedings of the 42nd annual Design Automation Conference
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Generation of broadside transition fault test sets that detect four-way bridging faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Forming N-detection test sets without test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test vector chains for increased targeted and untargeted fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On Detection of Bridge Defects with Stuck-at Tests
IEICE - Transactions on Information and Systems
Partitioned n-detection test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Forward-looking reverse order fault simulation for n-detection test sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On clustering of undetectable single stuck-at faults and test quality in full-scan circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-pattern n-detection stuck-at test sets for delay defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It was recently observed that, in order to improve the defect coverage of a test set, test generation based on fault models such as the single-line stuck-at model may need to be augmented so as to derive test sets that detect each modeled fault more than once. In this work, we report on test pattern generators for combinational circuits that generate test sets to detect each single line stuck-at fault a given number of times. Additionally, we study the effects of test set compaction on the defect coverage of such test sets. For the purpose of experimentation, defect coverage is measured by the coverage of surrogate faults, using a framework proposed earlier. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction if the test set is computed using appropriate test generation objectives. Moreover, two test sets generated using the same test generation objectives, except that compaction heuristics were used during the generation of one but not the other, typically have similar defect coverages, even if the compacted test set is significantly smaller than the noncompacted one. Test generation procedures and experimental results to support these claims are presented