X-masking during logic BIST and its impact on defect coverage

Authors:
Yuyi Tang;Hans-Joachim Wunderlich;Piet Engelke;Ilia Polian;Bernd Becker;Jürgen Schlöffel;Friedrich Hapke;Michael Wittke
Affiliations:
Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany;Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany;Institute for Computer Science, Albert-Ludwigs-University, Freiburg i. Br., Germany;Institute for Computer Science, Albert-Ludwigs-University, Freiburg i. Br., Germany;Institute for Computer Science, Albert-Ludwigs-University, Freiburg i. Br., Germany;Philips Semiconductors GmbH Design Technology Center, Hamburg, Germany;Philips Semiconductors GmbH Design Technology Center, Hamburg, Germany;Philips Semiconductors GmbH Design Technology Center, Hamburg, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.