On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Multiple test set generation method for LFSR-based BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan chain organization for embedded diagnosis
Proceedings of the conference on Design, automation and test in Europe
ModelSim verification tool in testing cores-based system-on-chips
MIC '08 Proceedings of the 27th IASTED International Conference on Modelling, Identification and Control
Evolution of self-diagnosing hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Suitability of various low-power testing techniques for IP core-based SoC: a survey
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |