Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
Integration, the VLSI Journal - Special issue on VLSI testing
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Genetic Algorithm and Graph Partitioning
IEEE Transactions on Computers
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
IEEE Design & Test
Reusing Scan Chains for Test Pattern Decompression
ETW '01 Proceedings of the IEEE European Test Workshop (ETW'01)
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Fault detection and diagnosis with parity trees for space compaction of test responses
Proceedings of the 43rd annual Design Automation Conference
BCH-based Compactors of Test Responses with Controllable Masks
ATS '06 Proceedings of the 15th Asian Test Symposium
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finite memory test response compactors for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Diagnosis With Convolutional Compactors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
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Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.