Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Error-control coding for computer systems
Error-control coding for computer systems
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
Journal of Electronic Testing: Theory and Applications
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan chain organization for embedded diagnosis
Proceedings of the conference on Design, automation and test in Europe
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper a new diagnosis method for scan designs with many scan-paths based on error correcting linear block codes with N information bits and K control bits is proposed, where N is the number of scan-paths. The new approach can be implemented on a modified STUMPS-architecture. In diagnosis mode the test has K times to be repeated. In the K repetitions of the test the outputs of the scan-paths are connected to a con.gurable signatureregister (with disconnected feedback logic) according to the coefficients of the K syndrome equations of the code. By monitoring the one-dimensional output sequence of the configurable signature register the failing scan-cells in the different scan-paths can be identified with the resolution of the selected error correcting code. Since for the relevant codes, e.g.(shortened) Hamming codes, T-error correcting BCH-code, the ratio {K \over N} decreases very fast with an increasing number N the method is useful for a large number of scan-paths.