A case study on the implementation of the Illinois Scan Architecture

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

Proceedings of the 39th annual Design Automation Conference

Extending OPMISR beyond 10x Scan Test Efficiency

IEEE Design & Test

Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits

Journal of Electronic Testing: Theory and Applications

ATPG versus Logic BIST -Now and in the Future

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

Journal of Electronic Testing: Theory and Applications

Test data compression using dictionaries with selective entries and fixed-length indices

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression

Proceedings of the conference on Design, automation and test in Europe - Volume 2

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Combining dictionary coding and LFSR reseeding for test data compression

Proceedings of the 41st annual Design Automation Conference

Adjustable Width Linear Combinational Scan Vector Decompression

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

RL-huffman encoding for test compression and power reduction in scan applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Efficient techniques for transition testing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Time-multiplexed compressed test of SOC designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Test data compression using efficient bitmask and dictionary selection methods

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Nine-coded compression technique for testing embedded cores in socs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Test data compression using four-coded and sparse storage for testing embedded core

ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II

Power problems in VLSI circuit testing

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths

Proceedings of the Conference on Design, Automation and Test in Europe