On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Low Transition LFSR for BIST-Based Applications
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
On Monte Carlo Testing of Logic Tree Networks
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
Transition density: a new measure of activity in digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Controlling or reducing power consumption during test and reducing test time are conflicting goals. Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to reduce test length with higher fault coverage in scan-BIST circuits. New test pattern generators (TPG) are proposed to generate weighted random patterns and controlled transition density patterns to facilitate efficient scan-BIST implementations. We achieve reduction in test application time without sacrificing fault coverage while maintaining any given test power constrain by dynamically adapting the scan clock, accomplished by a built-in hardware monitor of transition density in the scan register.