Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
IEEE Spectrum
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
Low Power BIST by Filtering Non-Detecting Vectors
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Power Dissipation During Testing: Should We Worry About it?
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation
Journal of Systems Architecture: the EUROMICRO Journal
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
Power problems in VLSI circuit testing
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to the circuit reliability. Moreover, it may be responsible for cost, performance verification as well as technology related problems and can dramatically shorten the battery life when on-line testing is considered. In this paper, we present a survey of the low power testing techniques that can be used to test VLSI systems. In the first part, the paper explains the problems induced by the increased power consumed during functional testing of a circuit, in either external testing or built-in self-test (BIST). Next, we survey state-of-the-art techniques that exist to reduce this power/energy consumption during test mode and allow non-destructive testing of the device under test.