The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Overall consideration of scan design and test generation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
An algorithm to reduce test application time in full scan designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
The Commercial Realization of Multi-Chip Modules Quo Vadimus
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Designing ASICs for Use with Multichip Modules
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Design-for-Testability Architecture for Multichip Modules
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Parity-Scan Design to Reduce the Cost of Test Application
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Optimal Sequencing of Scan Registers
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Low Power BIST for Wallace Tree-Based Fast Multipliers
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test generation costs, have been defined. It has been shown that the transition test generation cost is the minimum number of transitions required to test the corresponding stuck-at fault in fanout free circuits. This cost function is used for target fault selection while the other two functions are used to guide the backtrace and objective selection procedures of PODEM. The tests generated by the proposed ATPG decrease heat dissipation during test application by a factor of 2-23 for benchmark circuits.