SIESTA: a multi-facet scan design system
EURO-DAC '92 Proceedings of the conference on European design automation
A linear optimal test generation algorithm for interconnect testing
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
An approach to accelerate scan testing in IEEE 1149.1 architectures
ITC'94 Proceedings of the 1994 international conference on Test
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