An approach to accelerate scan testing in IEEE 1149.1 architectures

Authors:
Lee Whetsel
Affiliations:
Texas Instruments Inc.
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

Citing 3
Cited 0

Configuring multiple scan chains for minimum test time

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
The Test Access Port and Boundary-Scan Architecture

The Test Access Port and Boundary-Scan Architecture
Optimal Sequencing of Scan Registers

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level.