The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Introduction to algorithms
DFT Expert: Designing Testable VLSI Circuits
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A linear optimal test generation algorithm for interconnect testing
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Design of Partially Parallel Scan Chain
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A genetic approach to test application time reduction for full scan and partial scan circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Genetic Algorithms for Scan Path Design
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An approach to accelerate scan testing in IEEE 1149.1 architectures
ITC'94 Proceedings of the 1994 international conference on Test
Reduced scan shift: a new testing method for sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
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