On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Configuring multiple scan chains for minimum test time
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Overall consideration of scan design and test generation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An algorithm to reduce test application time in full scan designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Reduced Scan Shift: A New Testing Method for Sequential Circuit
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Serial-Scan Test-Vector-Compression Methodology
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique
ATS '96 Proceedings of the 5th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test application time reduction for sequential circuits with scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. A test subsequence consists of a sequence of primary input vectors, and a vector to be scanned-in before the input sequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences (the length of a test subsequence is the length of the input sequence included in it). The reductions in test application time of the proposed procedure are demonstrated through experimental results.