Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Assertion-Based Design
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Independent Test Sequence Compaction through Integer Programming
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
MYGEN: automata-based on-line test generator for assertion-based verification
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Model-driven test generation for system level validation
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques
IEEE Transactions on Computers
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On test generation with test vector improvement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enabling efficient post-silicon debug by clustering of hardware-assertions
Proceedings of the Conference on Design, Automation and Test in Europe
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Arithmetic transforms for compositions of sequential and imprecise datapaths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating Assertion Coverage With Adaptive Testbenches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Assertions are now widely used in verification as a means to help convey designer intent and also to simplify the detection of erroneous conditions by the firing of assertions. With this expressive modeling power, assertions could also be used for tasks such as helping to assess test coverage and even as a source for test generation. Our work deals with this last aspect, namely, assertion-based test generation. In this article, we present our compacted test generation scheme based on assertions. Novel compaction techniques are presented based on assertion clustering, test-path overlap detection and parallel-path removal. Our compaction approach is experimentally evaluated using nearly 300 assertions to show the amount of reduction that can be obtained in the size of the test sets. This ultimately has a positive impact on verification time in the quest for bugfree designs.