An algorithm to reduce test application time in full scan designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An approach to test compaction for scan circuits that enhances at-speed testing
Proceedings of the 38th annual Design Automation Conference
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Reducing test application time for full scan circuits by the addition of transfer sequences
ATS '00 Proceedings of the 9th Asian Test Symposium
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test application time reduction for sequential circuits with scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a new static compaction procedure for scancircuits that generates a test set with a reduced test applicationtime. The proposed procedure combines the advantagesof two earlier static compaction procedures, one thattends to generate large numbers of tests with short primaryinput sequences, and one that tends to generatesmall numbers of tests with long primary input sequences.The proposed procedure starts from a test set with a largenumber of tests and long primary input sequences, and itselects a subset of the tests and subsequences of their primaryinput sequences. It thus has the flexibility of findingan appropriate balance between the number of tests andthe lengths of the primary input sequences in order tominimize the test application time.