Functional test generation for full scan circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
An approach to test compaction for scan circuits that enhances at-speed testing
Proceedings of the 38th annual Design Automation Conference
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Computers
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
State persistence: a property for guiding test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. For every subsequence, it also accepts the vector to be scanned-in before the subsequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences. The reductions in test application time of the proposed procedure are demonstrated through experimental results.