DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
IEEE Design & Test
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In enhanced-scan circuits, a two-pattern test ti, tj for a transition fault can be obtained by using a test tj that detects a stuck-at fault, and preceding it by a test ti that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test ti, tj based on stuck-at tests ti and tj, it is not always possible to guarantee that the combination of ti and tj will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.