Introduction to algorithms
Combinatorial optimization
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Static compaction for two-pattern test sets
ATS '95 Proceedings of the 4th Asian Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On n-detection test sets and variable n-detection test sets for transition faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
On reducing both shift and capture power for scan-based testing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.