Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Proceedings of the 40th annual Design Automation Conference
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
Test Power Reduction with Multiple Capture Orders
ATS '04 Proceedings of the 13th Asian Test Symposium
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Proceedings of the conference on Design, automation and test in Europe
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
ETS '08 Proceedings of the 2008 13th European Test Symposium
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity
PRDC '11 Proceedings of the 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of Functional Broadside Tests for Transition Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signal-Transition Patterns of Functional Broadside Tests
IEEE Transactions on Computers
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This article studies the generation of low-power skewed-load tests such that the signal transitions (and line values) they create during their fast functional clock cycles match those of functional broadside tests. Functional broadside tests create functional operation conditions during their fast functional clock cycles. As a result, the signal transitions that occur during these clock cycles can also occur during functional operation. The procedure described in this article matches these signal-transitions on a line-by-line basis when generating low-power skewed-load tests. The procedure accepts a functional broadside test set for transition faults. In one of its basic steps, the procedure modifies a functional broadside test into a skewed-load test. This allows it to retain many of the signal transitions (and line values) of the functional broadside test in the skewed-load test. Experimental results for benchmark circuits demonstrate the extent to which it is possible to match the signal-transitions of skewed-load tests with those of functional broadside tests while achieving the high transition fault coverage that is typical of skewed-load tests.