On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Proceedings of the conference on Design, automation and test in Europe
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
Scan-Based Tests with Low Switching Activity
IEEE Design & Test
Variation-Tolerant, Power-Safe Pattern Generation
IEEE Design & Test
Methodology for low power test pattern generation using activity threshold control logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On reducing both shift and capture power for scan-based testing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells
Journal of Electronic Testing: Theory and Applications
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEICE - Transactions on Information and Systems
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph theoretic approach for scan cell reordering to minimize peak shift power
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Gating internal nodes to reduce power during scan shift
Proceedings of the 20th symposium on Great lakes symposium on VLSI
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Switching activity as a test compaction heuristic for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compression-aware capture power reduction for at-speed testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
Controlling peak power consumption during scan testing: power-aware DfT and test set perspectives
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
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It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.