Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Scan Power Reduction Through Test Data Transition Frequency Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Toggle-Masking for Test-per-Scan VLSI Circuits
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gating internal nodes to reduce power during scan shift
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Test patterns of multiple SIC vectors: theory and application in BIST schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Gating of the outputs of a portion of the scan cells (partial gating) has been recently proposed as a method for reducing the dynamic power dissipation during scan-based testing. We present a new systematic method for selecting, under area and performance design constraints, the most suitable for gating subset of scan cells as well as the proper gating value for each one of them, aiming at the reduction of the average switching activity during testing. We show that the proposed method outperforms the corresponding already known methods, with respect to average dynamic power dissipation reduction.