Low Power BIST by Filtering Non-Detecting Vectors
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A New BIST Architecture for Low Power Circuits
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power/Energy BIST Scheme for Datapaths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Low Power Pseudo-Random BIST Technique
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A new test pattern generator for high defect coverage in a BIST environment
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Low-Transition Test Pattern Generation for BIST-Based Applications
IEEE Transactions on Computers
A new low energy BIST using a statistical code
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new low power test pattern generator using a variable-length ring counter
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DS-LFSR: a BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single-input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are evaluated. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.