Survey of Low-Power Testing of VLSI Circuits

Authors:
Patrick Girard
Affiliations:
-
Venue:
IEEE Design & Test
Year:
2002

Citing 33
Cited 66

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QC-fill: an X-fill method for quick-and-cool scan test

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Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits

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Abstract

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. The article ends with a discussion of the opportunity to use such techniques in varying situations.