A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Testability Features of the 3rd Generation Coldfire® Family of Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
An Analysis of Powe Reduction Techniques in Scan Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Temperature-aware test scheduling for multiprocessor systems-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
DFT and minimum leakage pattern generation for static power reduction during test and burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
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In today's large designs, especially large SOC(system-on-a-chip) designs, vector volume for a singlecore could dominate the memory resources of the targettester and leave little or no room for other vectors. Tothis end, delivery of an "optimized" or "reduced" vectorset, without any loss of coverage, is preferred. Onecommercial means of delivering an optimized vector set isto compress the vectors during vector generation.Another applicable solution is to understand theoverlapping faults among various fault models andremove them from the fault lists for certain pattern types.The main problem with these optimization approaches isthat compressed vectors create more switching activities,which could potentially cause average power dissipation,instantaneous and peak power during test to besignificantly higher than normal operation. Test power issuch a big concern in large SOC designs that the powerassociated with the "reuse" vectors must be understood.This paper presents a case study of a Motorola Version 3ColdFire® microprocessor core, with a focus on thevarious vector optimizations and their ramifications ontest power.