A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Journal of Electronic Testing: Theory and Applications
THE TESTABILITY FEATURES OF THE MCF5407 CONTAINING THE 4TH GENERATION COLDFIRE® MICROPROCESSOR CORE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ON-THE-SHELF CORE PATTERN METHODOLOGYFOR COLDFIRE® MICROPROCESSOR CORES
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
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A description of the DFT and Test challenges faced, andthe solutions applied, to the newest member of the Cold-Fire® microprocessor family, the MCF5307, is described.The MCF5307 is the 脼rst member of the family to haveon-chip, PLL-sourced, dual clock domains where the businterface and the internal core microprocessor operate atdifferent, but selectable, frequency ratios; and the internal microprocessor core of the MCF5307 was designedas a separate stand-alone core that contained multipleembedded memory arrays. The DFT challenges and solutions described involve the development of the at-speedAC scan test architecture and scan vectors in a multipleclock domain environment; the application of memoryBIST to multiple embedded memories in a cost effectivemanner; and the handling of an on-chip PLL clocksource.