Designing and Verifying Embedded Microprocessors
IEEE Design & Test
Test Development for Second-Generation ColdFire Microprocessors
IEEE Design & Test
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Effective Path Selection for Delay Fault Testing of Sequential Circuits
Proceedings of the IEEE International Test Conference
THE TESTABILITY FEATURES OF THE MCF5407 CONTAINING THE 4TH GENERATION COLDFIRE® MICROPROCESSOR CORE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ON-THE-SHELF CORE PATTERN METHODOLOGYFOR COLDFIRE® MICROPROCESSOR CORES
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Testability Features of the 3rd Generation Coldfire® Family of Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Performance verification of high-performance ASICs using at-speed structural test
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Editor's note: Commercial EDA tools support critical-path identification, as well as transition and path delay ATPG. But how can you narrow down the target faults or paths, and which ATPG technique should you use? The authors present a practical methodology addressing these important questions.驴Ken Butler, Texas Instruments