Implementing 1149.1 in the PowerPCTM RISC Microprocessor Family
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Detection of "Undetectable" Faults Using IDDQ Testing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors
ITC '97 Proceedings of the 1997 IEEE International Test Conference
The Direct-Mapped Instruction Cache for ColdFire Processors
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Test Development for a Third-Version ColdFire Microprocessor
IEEE Design & Test
Scan vs. Functional Testing - A Comparative Effectiveness Study on Motorola's MMC2107TM
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
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A case study of the development of the design for test methodology of the second generation of the ColdFire(r) Microprocessor family is described from the viewpoint of goals, initial strategy, and implementation. Methodology includes at-speed scan path design, path delay testing, IDDQ, and direct access test modes for embedded memories. Scan tests are applied with timing identical to that specified for peak performance normal operation.